This invention relates to electronic circuits used to control the gain or attenuation of an electronic signal and, in particular, to techniques for improving the performance of those circuits which operate in a mode known in the art as "class A" with respect to bandwidth, control feed-through, distortion, dynamic range and thermal stability when they are fabricated as monolithic integrated circuits. Such devices are commonly known as voltage controlled amplifiers (VCA's), voltage controlled attenuators (VCAtt's), automatic gain controls (AGC's) or electronic analog multipliers.
As used herein, the term "gain cell" refers to a circuit block for controlling the gain of an electronic signal and having at least one input terminal, one output terminal and one control terminal. Multipliers disclosed in early prior art utilized a simple gain cell comprising one emitter coupled, emitter driven pair of transistors, also known as a differential current steering circuit, wherein a signal current is supplied to an input terminal formed by the joined emitters of the transistor pair, and an output is derived from one or the other of the collectors of the pair, the magnitude of which is determined by a control voltage applied between the two transistor bases.
Multiplier circuits thus formed rely on two well established principles. The first states that, with the exception of small leakage currents, the sum of the currents out of the two collectors will always be equal to the current applied to the joined emitters, or stated as an equation, EQU I .sub.IN =I .sub.OUT 1 +I.sub.OUT 2. [1]
The second, known as the principle of "current steering", states that the current applied to the joined emitters of a differential pair will be distributed (steered) predictably between the collectors of the two transistors as determined by the control voltage applied between their bases. The ratio of the outputs from the two collectors is expressed by the equation ##EQU1## V.sub.c =the control signal between the transistor bases, and V.sub.t =the semiconductor thermal voltage kT/q=26 mV at 302 degrees Kelvin, and where
k is Boltzman's constant, PA1 T is the temperature in degrees Kelvin, and PA1 q is the charge on an electron.
As noted, two outputs are possible from this current steering circuit, one from each collector of the pair, and, since the total output current is constant, as the control voltage causes the signal to increase at one output, it is attenuated at the other. The actual polarity of the control voltage is dependent upon the polarity of the transistors comprising the gain cell as well as the base to which the control voltage is referred. For the convenience of further discussion, a positive value for V.sub.c shall be defined as causing loss or attenuation at the output of the multiplier.
The current gain of such gain cells, A, is defined by the ratio of the current from one of the outputs to the input current and is expressed by the equation ##EQU2##
One limitation associated with these simple a gain cells is that, since all of the transistors comprising such a gain cell are of one polarity, the input signal to it must likewise be unipolar. To accommodate a bipolar input signal, a D.C. bias equal to one half of the maximum allowable input signal current can be summed with the input signal, resulting in a composite signal which ranges between the minimum and maximum allowable unipolar input current.
A problem with this technique is that, as the gain of the circuit is varied, the D.C. bias present in the input signal is modulated along with the desired bipolar signal, resulting in the presence of an undesirable changing D.C. component in the output signal. Another problem with such gain cell topologies is the presence of significant levels of even order harmonic distortion products in the output signal.
More advanced circuits utilize matched pairs of current steering circuits, also called balanced or four transistor gain cells or gain quads. In such circuits, the corresponding bases of each transistor of each differential pair are joined such that the two differential pairs are controlled in tandem, and an output signal is derived as the difference of the two signals from the corresponding collectors of each differential pair.
The advantages of constructing gain control circuits using four transistor gain cells are well known in the art. One such advantage is that the second transistor pair provides a like changing D.C. value which can be subtracted from the output signal to cancel the above noted D.C. changes. Another improvement is realized when the input signal is applied differentially between the inputs of the two differential pairs and later combined differentially at the output. Then, the previously noted even order distortion products present in the output signal of each of the pairs are also canceled. These advantages are best realized when such circuits are fabricated as monolithic integrated circuits, which assures a higher degree of device matching than is otherwise possible. Further discussion of gain cells will refer only to these latter topologies.
When a signal is simply applied to the input of a gain cell, and an output is derived from one or the other output terminal, the circuit is known as a VCAtt or AGC attenuator. In the article, "An Integrated Wide Band Variable Gain Amplifier With Maximum Dynamic Range" (IEEE Journal of Solid State Circuits, Vol. SC-9, No. 4, Aug., 1974), Sansen and Meyer reported that distortion and noise in the balanced AGC are due primarily to the base resistance (R.sub.b) of transistors of the gain quad. They further reported that, in the balanced AGC, for very low values of base resistance, the linearity of the output signal is determined almost exclusively by the linearity of the input current sources which drive each of the emitter coupled pairs. Since this base resistance also represents a linear error term in the otherwise logarithmic characteristic of a b-e junction, a lower value for R.sub.b is also desirable in order to realize a circuit which more closely adheres to the ideal control law described by equation [3]. Low base resistance can be achieved by fabricating so-called "large geometry" transistors having a large emitter area or by connecting several transistors of smaller geometry in parallel.
Typically, the input stage used in balanced gain cells of prior art comprises a base driven differential transistor pair to derive the required differential signal currents. This input topology suffers restricted dynamic range because the maximum amplitude of the input signal is severely limited before the onset of unacceptable levels of distortion. The inclusion of emitter resistors results in an input stage having controlled gain and lower distortion in each signal path. However, when such a stage is driven from an unbalanced input signal, it exhibits less than ideal symmetry between the two signals. This, in turn, reduces the desired cancellation of undesired harmonic products in the output of the multiplier.
Applicant's prior U.S. Pat. No. 4,155,047 describes a balanced AGC topology comprising gain cell transistors having very low base resistance in combination with a pair of highly linearized input current sources which overcomes most of these problems. In this circuit, each input transistor is configured as a common base circuit, and an input signal current and an appropriate bias current are summed into each of the emitters. The dynamic range of this input circuit is further increased by actively linearizing the b-e junction of each input transistor by placing it in the feedback loop of an operational amplifier circuit, thus allowing a much larger input signal to be applied to each half of the input stage without inducing distortion. This patent also cites the further advantage of idealizing the loads on the collectors of the gain controlling transistors to maintain constant performance over the operating range of the circuit. Circuits so constructed have demonstrated a dynamic range greater than 116 Db (20 Khz bandwidth) with worst case harmonic distortion less than 0.03 percent.
The only remaining drawback to this input circuit is that, in the case of a unbalanced input signal, additional circuitry must be employed to derive the required balanced, differential signals before they are applied to the input stage. Prior patents describing balanced AGC attenuator circuits and improvements thereon include U.S. Pat. Nos. 3,641,450 (Lunn), 3,684,9764 (Soloman et al), 3,999,141 (Cochran et al) and 4,471,320 (Frey).
Equation [3] reveals one disadvantage of the AGC attenuator topology in some applications, since the maximum current gain of the multiplier, itself, is unity. Stated otherwise, it exhibits only loss (attenuation) with respect to the input signal. Thus, when an application requires a maximum current gain greater than unity, an additional gain stage must follow the gain cell, which also amplifies noise and other unwanted residual artifacts inherent in the gain cell, itself, along with the output signal.
Another potential disadvantage of the AGC topology can be observed from equation [3] in that it describes a control law which is neither linear nor purely exponential. With a linear control law, a linear unit of change in the control signal causes a linear change in the gain of the circuit. However, in many applications, it is desirable that an exponential relationship exist between the control and signal inputs, wherein a linear unit of change in the control signal causes a ratiometric change in the amplitude of the output signal. For example, in audio applications, where the standard unit of relative loudness, the decibel (Db), is exponential in nature, it is functionally useful to control the relative gain of a circuit exponentially with a signal scaled in linear units, e.g. Db/volt. The gain of such a circuit is described by the equation ##EQU3##
Although both equations [3] and [4] derive from the well established logarithmic characteristic of the b-e junction of its component transistors, the presence of the "1+" term in equation [3] causes a departure from an exponential control characteristic for small values of attenuation in the AGC.
In addition to a functionally convenient control law, most circuits with the control law described by equation [4] have the further advantage that they can exhibit both gain and loss with respect to the input signal. Such circuits disclosed in the prior art are of the general type known as "log/antilog" VCA's. They are so named because they first derive the log of the input signal; they then sum a linear control voltage with this logged signal and then derive the antilog (exponent) of that sum, as expressed by the equation EQU I .sub.OUT =-exp (log I .sub.IN +[.sup.V c/V.sub.t ]). [5]
The minus sign appears in the above expression because, typically, the output signal current from these circuits is inverted with respect to the input signal. Prior patents describing the basic theory and operation of log/antilog VCA's and improvements thereon include U.S. Pat. Nos. 3,532,868 (Embley), 3,714,462 (Blackmer), 4,225,794 (Buff), 4,331,931 (Adams) and 4,341,962 (Buff).
In comparing the noise performance of AGC and log/antilog multipliers using gain cells with equal noise characteristics, the AGC circuit is inherently quieter in applications where a gain greater than unity is not required. This is because, in a log/antilog circuit, the noise component of the gain cell itself is fed back to the input of the circuit.
As shown in U.S. Pat. Nos. 4,331,929 (Yokoyama) and 4,341,962, previously cited, the noise performance of a gain cell can be improved by placing one or more diodes or diode-connected transistors in series with the emitter of each primary transistor of each pair to form a composite or "effective" transistor device. This has the effect of lowering the transconductance of the pair and, thereby, its noise contribution. Each such effective transistor behaves as a single device having the polarity of the primary transistor and an effective base-emitter (b-e) voltage equal to the sum of the b-e voltage of the primary transistor plus the b-e or diode voltage of each secondary device. Implicit in this technique is that the control voltage required to effect a given change in the gain of the circuit is also determined by this effective b-e voltage. For convenience, henceforth, the terms "transistor" and "effective transistor" may be used interchangeably to denote a single or a composite transistor device.
Many of the log/antilog VCA circuits cited above operate as "class B" or "class AB" circuits. In a class B circuit, positive and negative portions of the signal are processed by different devices or signal paths within the circuit, each of which is held out of conduction (turned off) when the opposite signal path is active, and both of which are turned off when no input signal is present. In a class AB circuit, each half of the circuit is biased slightly on to create a somewhat smoothed crossover region in which both halves of the circuit are active.
The disadvantages of class B and class AB operation are well documented in the prior art. These include crossover distortion and modulation noise. Another problem common to such circuits arises because, as each of the signal paths alternately turns on and off, their associated components correspondingly heat and cool. This results in signal induced thermal transients within the circuit which have been demonstrated to induce distortion products in the output signal. A further problem with these circuits arises because the amplitude of the input signal determines operating current within each path of the gain cell. Thus, when the input signal is very low in amplitude, the operating current in the transistors comprising the gain cell is also very low, which, in turn, has the effect of reducing the bandwidth of the circuit under low signal conditions.
In contrast, the present invention, as well as all of the AGC circuits and several of the latter log/antilog circuits in the above cited patents, operate as class A circuits, wherein sufficient D.C. bias is present on all of the transistors in the signal path that they remain in conduction under all normal conditions of operation. The advantages of class A operation include freedom from crossover distortion and signal induced thermal transients, as well as minimization of modulation noise, previously noted.
All of the cited class A circuits utilize two current steering circuits, each comprising a differential transistor pair. Furthermore, in all of the balanced AGC circuits and one of the log/antilog circuits, all of the effective transistors are of the same polarity. While this ensures close matching of the electrical characteristics of the two signal paths, the output signal is usually stated to be balanced, or differential, in nature. In most of the prior art, some means, such as a transformer or a differential amplifier, is then used to recombine the two outputs or otherwise obtain the desired cancellations in the output signal.
As shown in U.S. Pat. Nos. 4,004,141 (Curtis) and 4,331,929, previously cited, a circuit commonly used in the design of monolithic operational amplifiers and known in the art as a "current mirror" provides another means of converting the balanced output from a gain cell to a single-ended signal current while maintaining a idealized load on each output terminal.
The latter patent also illustrates another technique, common in operational amplifier design, wherein another transistor is connected in series with the input of each current mirror in what is know in the art as a "cascode" configuration. So connected, the base of each cascode transistor is biased such that its emitter is at or near ground. Thus, the collector of each transistor which is feeds the input of a current mirror operates under conditions similar to the corresponding device which is connected to a circuit output terminal.
Unlike the balanced AGC circuits of the prior art, all but one of the cited class A log/antilog circuits use dissimilar differential pairs in which the effective transistors comprising each pair opposite in polarity from those comprising the other. In such gain cells, the appropriate collectors from each of the pairs are simply tied together to form the output and feedback terminals of the gain cell, with signals in the form of currents having a quiescent value centered between the two power supplies.
In theory, this configuration maintains the advantages of canceling unwanted D.C. and even order harmonic products, and it has the advantage of providing an output signal which is more convenient to use in applications where it is desirable to sum the output from a number of such gain cells. A single ended current output signal also allows for a simpler realization of such functions as some forms of electronically controlled filter circuits.
Although, for any given gain condition, these circuits do not exhibit the transient distortion problems of class B and class AB designs, the unmatched characteristics of their dissimilar devices typically cause other errors in the output signal. These errors occur for two reasons:
First, as the gain of the multiplier changes in response to a control signal, electrical dissimilarities in the unlike devices can cause the control characteristic of one of the current steering circuits not to match that of the other. Second, as more or less current is steered to the output or feedback terminal through each path of the gain cell, relative heating and cooling of the dissimilar devices occurs, resulting in thermally induced mismatches between the two signal paths. Under such conditions, the otherwise complementary error components present in each half of the circuit do not cancel when the two outputs are recombined.
One such error is a shift in the D.C. base line of the output signal, either as the gain of the circuit is varied or in response to external thermal changes, resulting in "control feed-through", an undesirable artifact in the output signal in response to changes in the control signal. Another such error is thermally induced static or transient residual distortion products in the output signal. Although many of these errors can be trimmed out for a limited range of operating conditions, no means is presently available to cause even monolithic transistors of opposite polarity to track each other perfectly under all electrical and thermal conditions of operation.
When an AGC attenuator is included in the feedback loop of an operational gain circuit, the "1+" term in equation [3] drops out, and a class A multiplier having a purely exponential gain control law is realized. This is shown as follows:
If the signal I .sub.OUT 1 from output 1 is returned to the inverting input of the input stage as feedback current I .sub.FB, and the signal I .sub.OUT 2 from output 2 is defined as output signal I .sub.OUT, then EQU I .sub.OUT 1 =I .sub.FB =-I .sub.IN, and [6] EQU I .sub.OUT 2 =I .sub.OUT . [7]
Substituting equations [6] and [7] in equation [2], ##EQU4##
Inverting both sides of the equation gives ##EQU5## which is the same as equation [4], except for the minus sign, and is the desired result, referred to equation [5]. As will be shown in the preferred embodiments, with minor modification, it is further possible to derive an output signal current which is non-inverted with respect to the input signal.
These circuits avoid the cited problems associated with gain cells comprising dissimilar devices. However, operational circuits rely on negative feedback to reduce any distortion generated within the circuit, itself. The amount by which this internal (open loop) distortion can be reduced is a function of the difference between the open loop and closed loop gain of the circuit, which, in these circuits, varies as a function of the instantaneous gain of the multiplier, and by any delays which may exist in the feedback path. Such delays also pose constraints on the high frequency stability and the transient performance that can be attained by the circuit. Thus, the performance of the multiplier circuits shown in the prior art is limited by the open loop distortion, noise and bandwidth characteristics of the gain cell, itself.
If one of the two output signals from a balanced AGC attenuator is subtracted from the other, the resulting output signal current ranges between +I .sub.IN and -I .sub.IN as the control signal goes from +V.sub.c max to -V.sub.c max. Furthermore, since the signal from each path of the gain cell is equal to, and opposite in polarity from the other, when V.sub.c =0, the resulting output signal current also equals 0.
This control transfer function can be easily obtained by cross-connecting the respective first and second output terminals from one current steering circuit to the respective second and first output terminals of the second. This connection describes a third multiplier circuit commonly know as a four quadrant multiplier or balanced modulator demodulator, the gain of which is described by the equation ##EQU6##
Although equation [10] is highly nonlinear, such multipliers are widely used in applications such as phase detectors in phase locked loops and in various frequency and amplitude modulation and demodulation circuits. Also, with additional linearizing circuitry, the control function of a four quadrant multiplier can be made to be highly linear and independent of temperature. Such techniques are described by Barrie Gilbert in "A Precise Four-Quadrant Multiplier with Subnanosecond Response" (IEEE Journal of Solid State Circuits, Vol. SC-3, No. 4, Dec., 1968).
It has been shown that a balanced AGC attenuator, an exponentially controlled multiplier and a four quadrant multiplier all can be implemented as applications of the same basic balanced gain cell. It is the specific method of interconnecting the gain cell with its surrounding circuitry that determines which type of multiplier is realized. Therefore, improvements in the performance of the gain cell, itself, over prior art now result in improvements in the performance of all of these types of multiplier circuits.